By Topic

Hybrid cache architecture for high-speed packet processing

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $33
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Z. Liu ; Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing ; K. Zheng ; B. Liu

The exposed memory hierarchies employed in many network processors (NPs) are expensive in terms of meeting the worst-case processing requirement. Moreover, it is difficult to effectively utilise them because of the explicit data movement between different memory levels. Also, the effectiveness of traditional cache in NPs needs to be improved. A memory hierarchy component, called split control cache, is presented that employs two independent low-latency memory stores to temporarily hold the flow-based and application-relevant information, exploiting the different locality behaviours exhibited by these two types of data. Just like conventional cache, data movement is manipulated by specially designed hardware so as to relieve the programmers from the details of memory management. Software simulation shows that compared with conventional cache, a performance improvement of up to 90% can be achieved by this scheme for OC-3c and OC-12c links

Published in:

IET Computers & Digital Techniques  (Volume:1 ,  Issue: 2 )