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An SRAM Design in 65-nm Technology Node Featuring Read and Write-Assist Circuits to Expand Operating Voltage

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6 Author(s)
Pilo, H. ; IBM Syst. & Technol. Group, Essex Junction, VT ; Barwin, C. ; Braceras, G. ; Browning, C.
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This paper describes a 32-Mb SRAM that has been designed and fabricated in a 65-nm low-power CMOS Technology. The 62-mm2 die features read-assist and write-assist circuit techniques that expand the operating voltage range and improve manufacturability across technology platforms. Hardware measurements demonstrate the fail-count improvements achieved by integrating these techniques. The decrease in fail-count provides a 100-mV improvement of VDDMIN during the read operation. Write operations are also improved, especially with weak NFET cell transistors. The circuit techniques have been replicated on a 72-Mb stand-alone standard SRAM product where the area overhead from the additional circuits is approximately 4%. The 32-Mb SRAM has also been successfully migrated to other yield-learning SRAMs in 45-nm bulk and SOI technologies with minimum circuit changes

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Solid-State Circuits, IEEE Journal of  (Volume:42 ,  Issue: 4 )