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A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits

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16 Author(s)
Ohbayashi, S. ; Renesas Technol. Corp., Hyogo ; Yabuuchi, M. ; Nii, K. ; Tsukamoto, Y.
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In the sub-100-nm CMOS generation, a large local Vth variability degrades the 6T-SRAM cell stability, so that we have to consider this local variability as well as the global variability to achieve high-yield SRAM products. Therefore, we need to employ some assist circuits to expand the SRAM operating margin. We propose a variability-tolerant 6T-SRAM cell layout and new circuit techniques to improve both the read and the write operating margins in the presence of a large Vth variability. By applying these circuit techniques to a 0.494-mum2 SRAM cell with a beta ratio of 1, which is an extremely small cell size, we can achieve a high-yield 8M-SRAM for a wide range of Vth values using a 65-nm low stand-by power (LSTP) CMOS technology

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:42 ,  Issue: 4 )

Date of Publication:

April 2007

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