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The determination of electrical properties of interconnects represents a critical design and analysis problem in the high-speed integrated very large-scale integration (VLSI) circuit in order to minimize signal distortion due to propagation delay and dispersion. In order to accomplish this, it is necessary to analyze and model the broad-band characteristics of submicrometer interconnects since the signals tend to exhibit both the short rising and falling times. Today, most extraction and delay analysis tools are limited to RC networks leaving an inherent unpredictability in the design process where inductive and substrate effects are suspected. However, the effect of a silicon substrate, which is negligible at low frequency, has a prevalent effect on the characteristics of lines during the operation of high-speed chips. One result of this study is to give a criteria that can be used to determine that a range exist for which inductance and substrate effects are not negligible, and which nets require a complete transmission line model.