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CMOS RF ICs continue their transition from academic curiosities to practical devices. Recent milestones at the device- and building block-level include: Noise figures for single-ended LNAs of ~ldB in the low-GHz range; fully integrated oscillators with phase noise compliant with GSM specifications at under lOmW power consumption; 5GHz injection-locked frequency dividers with sub-mW power consumption and large (~30%) tuning range; MOSFET ring mixers with over lOdBm 11P3 and "zero" power consumption; shielded spiral and helical inductors with improved Q; accumulation-mode MOS varactors with Q-frequency products in excess of 100-200GHz and tuning ratios approaching 2:1; fixed lateral flux capacitors with still higher Q-f products; coplanar transmission lines with <0.3dB/mm attenuation at 50GHz; microwave-compatible ESD structures; and constant-gm biasing for process independence. These advances have combined to enable a single-chip GPS receiver in 0.5Â¿m to exhibit 2.8dB overall NF, 57dB SFDR at 115mW, and a 5GHz HIPERLAN receiver to exhibit 5dB NF at <45mW using a 0.25Â¿m technology. Scaling forces that are already firmly in place will continue to drive still greater improvements in performance.