By Topic

Enhanced Strain Effects in 25-nm Gate-Length Thin-Body nMOSFETs With Silicon–Carbon Source/Drain and Tensile-Stress Liner

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

7 Author(s)
Kah-Wee Ang ; Dept. of Electr. & Comput. Eng., Nat. Univ. of Singapore ; King-Jien Chui ; Chih-Hang Tung ; Balasubramanian, N.
more authors

We report the demonstration of 25-nm gate-length LG strained nMOSFETs featuring the silicon-carbon source and drain (Si1-yCyS/D) regions and a thin-body thickness T body of ~18 nm. This is also the smallest reported planar nMOSFET with the Si1-yCyS/D stressors. Strain-induced mobility enhancement due to the Si1-yCy S/D leads to a significant drive-current IDsat enhancement of 52% over the control transistor. Furthermore, the integration of tensile-stress SiN etch stop layer and Si1-yC yS/D extends the IDsat enhancement to 67%. The performance enhancement was achieved for the devices with similar subthreshold swing and drain-induced barrier lowering. The Si1-y CyS/D technology and its combination with the existing strained-silicon techniques are promising for the future high-performance CMOS applications

Published in:

Electron Device Letters, IEEE  (Volume:28 ,  Issue: 4 )