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A method and a topology focusing on output power flatness over a given bandwidth, combined with inherent harmonic rejection is presented and applied to a family of MMIC designs. Several single frequency multiplier designs seeking high multiplication gain or output power for a given device have already been reported. The approach proposed in this paper focuses on frequency bandwidth, output power or gain flatness and sufficient inherent rejection of undesired harmonics in order to avoid the need for extensive external filtering at the output. Atopology for doublers and quadruplers is derived and applied to several designs in MMIC technology for space equipments. A comparison between harmonic balance simulations and measurements is presented at the end of this paper.