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As system-level interconnect incurs increasing penalties in latency, round-trip cycle time and power, and as timing-variability becomes an increasing design challenge, there is renewed interest in using two-phase delay-insensitive protocols for global system-level communication. However, in practice, when designing asynchronous systems, it is extremely inefficient to build local computation nodes with two-phase logic, hence four-phase computation blocks are typically used. This paper proposes a new architecture, and circuit-level implementations, for a family of asynchronous protocol converters, which efficiently convert between two- and four-phase protocols, thus facilitating system design with robust global two-phase protocols and local four-phase protocols. The main focus is on a level-encoded dual-rail (LEDR) two-phase protocol for global communication, and a four-phase return-to-zero (RZ) protocol for asynchronous computation blocks. However, with small modifications, the converters are extended to handle other common four-phase protocols, such as 1- of-4 and single-rail bundled data. The converters are highly robust, with almost entirely quasi delay- insensitive implementations, yet exhibit high performance and modest area overhead. Initial post-layout simulations in a 0.18 micron TSMC process are provided, both assuming a small computation block (8times8 combinational multiplier) as well as an empty computation block (FIFO stage).