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Demystifying Data-Driven and Pausible Clocking Schemes

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2 Author(s)
Robert Mullins ; University of Cambridge, UK ; Simon Moore

VLSI systems are often constructed from a multitude of independently clocked synchronous IP blocks. Unfortunately, while a synchronous design style may produce efficient block level implementations it does little to support their composition. The addition of asynchronous interfaces to each synchronous block is one way to simplify and strengthen their integration. Asynchronous interfaces allow blocks to be composed without the need to consider synchronisation failure rates, permit data-driven operation and provide greater freedom when designing on-chip buses and networks. This paper surveys the significant body of published work in this area. We highlight similarities between schemes that are often concealed by differences in specification or circuit style. We also present new local clock implementations and provide solutions to mitigate the effect of clock-tree insertion delays. The ultimate goal of this work is to permit multi-clock synchronous systems to be composed simply, robustly and efficiently.

Published in:

13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07)

Date of Conference:

12-14 March 2007