Notification:
We are currently experiencing intermittent issues impacting performance. We apologize for the inconvenience.
By Topic

On-chip samplers for test and debug of asynchronous circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Liu, F. ; Sun Microsyst. Labs., Menlo Park, CA ; Ho, R. ; Drost, R. ; Fairbanks, S.

On-chip high-bandwidth sampling circuits supplement traditional test and debug techniques by non-invasively probing analog voltages for off-chip measurement. Existing circuits rely on sub-sampling techniques and thus require a synchronous clock. We extend these ideas to asynchronous circuits by combining an analog sampling head with a variable delay element and activating this circuit with an asynchronously triggered event. Repeated triggering events with different delays emulate sub-sampling. Simulations in a 180 nm technology of SRAM timing margins and GasP control failure modes show this technique can probe asynchronous signals with high fidelity.

Published in:

Asynchronous Circuits and Systems, 2007. ASYNC 2007. 13th IEEE International Symposium on

Date of Conference:

12-14 March 2007