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A Parallel Progressive Refinement Image Rendering Algorithm on a Scalable Multithreaded VLSI Processor Array

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5 Author(s)
S. K. Nandy ; Indian Institute of Science, India ; Ranjani Narayan ; V. Visvanathan ; P. Sadayappan
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In this paper we develop a multithreaded VLSI processor linear array architecture to render complex environments based on the radiosity approach. The processing elements are identical and multithreaded. They work in Single Program Multiple Data (SPMD) mode. A new algorithm to do the radiosity computations based on the progressive refinement approach[2] is proposed. Simulation results indicate that the architecture is latency tolerant and scalable. It is shown that a linear array of 128 uni-threaded processing elements sustains a throughput close to 0.4 million patches/sec.

Published in:

Parallel Processing, 1993. ICPP 1993. International Conference on  (Volume:3 )

Date of Conference:

16-20 Aug. 1993