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Parallel FFT Algorithms for Cache Based Shared Memory Multiprocessors

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2 Author(s)
Kumar, A. ; Texas A&M University, USA ; Bhuyan, L.N.

Shared memory multiprocessors with cache require careful consideration of cache parameters while implementing an algorithm to obtain optimal performance. In this paper, we study the implementation of some existing FFT algorithms and analyze the number of cache misses based on the problem size, number of processors, cache size, and block size. We also propose a new FFT algorithm which minimizes the number of cache misses.

Published in:

Parallel Processing, 1993. ICPP 1993. International Conference on  (Volume:3 )

Date of Conference:

16-20 Aug. 1993

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