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A Stress-Relaxed Negative Voltage-Level Converter

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1 Author(s)
Tsiatouhas, Y.E. ; Dept. of Comput. Sci., Ioannina Univ.

In this brief, a new embedded negative voltage-level converter (level shifter) is presented. The proposed circuit can convert a positive input signal to a negative output signal with reduced or even without (depending on the application) voltage stress on the used MOS devices. The circuit has been designed in a 0.18-mum triple-well standard CMOS technology, using double-gate-oxide-thickness MOS transistors with an absolute maximum rating of 4.0 V, a nominal power supply of 1.8 V, and a required negative voltage of -3.3 V. Simulation results are provided to demonstrate the efficiency of the proposed topology. According to the results, 1.82-ns delay and 0.53-mW power consumption are reported

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Circuits and Systems II: Express Briefs, IEEE Transactions on  (Volume:54 ,  Issue: 3 )