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Fast- Frequency Offset Cancellation Loop Using Low-IF Receiver and Fractional-N PLL

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4 Author(s)
Sangho Shin ; Dept. of Electr. Eng. & Comput. Sci., Korea Adv. Inst. of Sci. & Technol., Daejeon ; Kyungmin Kim ; Kwyro Lee ; Sung-Mo Kang

This brief introduces a simple circuit solution to secure loop stability of an analog-domain fast-frequency offset cancellation loop (OCL). The OCL is composed of a low-IF receiver, phase-domain frequency offset detector (OD), and fractional-N phase-locked loop (PLL). Since the OCL uses a phase-domain OD, a stability concern is essentially needed for its practical use. From the frequency-domain analysis, a PLL bandwidth adaptation by controlling charge-pump currents is proposed to achieve a strong stability with phase-margin of more than 60deg. Additionally, a tradeoff between the OCL accuracy and hardware complexity is discussed, and a design example is shown for the 2.4-GHz ZigBee application. With 4-MHz IF, designed for an 0.18-mum CMOS process, our circuit takes 30 mus to reject the frequency offset of +200 kHz within the accuracy of plusmn5 ppm, with 60-DFFs for a time-to-digital converter

Published in:

IEEE Transactions on Circuits and Systems II: Express Briefs  (Volume:54 ,  Issue: 3 )