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A Design Procedure for All-Digital Phase-Locked Loops Based on a Charge-Pump Phase-Locked-Loop Analogy

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4 Author(s)
Kratyuk, V. ; Sch. of Electr. Eng. & Comput. Sci., Oregon State Univ., Corvallis, OR ; Hanumolu, P.K. ; Un-Ku Moon ; Mayaram, K.

In this brief, a systematic design procedure for a second-order all-digital phase-locked loop (PLL) is proposed. The design procedure is based on the analogy between a type-II second-order analog PLL and an all-digital PLL. The all-digital PLL design inherits the frequency response and stability characteristics of the analog prototype PLL

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Circuits and Systems II: Express Briefs, IEEE Transactions on  (Volume:54 ,  Issue: 3 )