Referenced Items are not available for this document.
This paper presents a FPGA-based video compression system (FVCS) and its testing interface system (TIS). The FVCS is designed in order to implement complex algorithms such as MPEG-4. TIS is implemented to facilitate functions' development. A high-end FPGA from Xilinx's Vertex-4 series has been used to perform the functions including video acquisition, compression and bit-stream transmission. FVCS implements an open architecture with a separate video lens module and can connect an optional extend memory system. Two compression solutions based on FVCS's architecture demonstrate the flexibility
Published in:
Signal Processing, 2006 8th International Conference on
(Volume:1
)
Date of Conference: 16-20 2006
- E-ISBN :
- 0-7803-9737-1
- Print ISBN:
- 0-7803-9736-3
- INSPEC Accession Number:
- 9464271
- Conference Location :
- Beijing
- Digital Object Identifier :
- 10.1109/ICOSP.2006.345485
- Product Type:
- Conference Publications
About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies
A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2013 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.
