On the Performance and Use of an Improved Source–Follower Buffer

An analysis of a proposed source-follower (SF)-based buffer circuit and its performance is presented. High linearity and wide bandwidth are achieved by the use of adaptive biasing of a SF transistor to mitigate the impact of the load current of the buffer and to speed up the settling behavior. The adaptive biasing is realized by means of a low gain current domain feedback that allows simultaneous scaling of the bias currents and signal bandwidth and hence enables the realization of power-efficient buffers for circuits that are used in varying conditions, such as analog-digital converters. The theory specifies the dominant distortion mechanisms, and thus, together with a noise analysis and a discussion of the design options, enables efficient design optimization. The simulation cases support the analysis and show that the proposed buffer topology enables a buffer to be constructed that has a ~75-dB spurious-free dynamic range, for example, with ~50-MHz signal bandwidth using 0.35-mum CMOS transistors