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Performance Metrics of a 5 nm, Planar, Top Gate, Carbon Nanotube on Insulator (COI) Transistor

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2 Author(s)
Alam, K. ; Dept. of Electr. Eng., California Univ., Riverside, CA ; Lake, Roger

The performance of a planar, 5 nm top gate, carbon nanotube on insulator (COI) field-effect transistor (COIFET) with source/drain underlaps is analyzed. The performance metrics of switching delay time and cutoff frequency are calculated. A 2 nm thick, relatively low-K, SiO 2 gate dielectric combined with a source/drain underlap geometry and insulating substrate minimizes the parasitic gate to source CGS and gate to drain CGD capacitances and results in a 23 fs switching delay time. The simplicity of the device design is required to satisfy the constraints of a self-assembly process. The device analyzed is also a scaled version of recently demonstrated CNTFETs on sapphire

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Nanotechnology, IEEE Transactions on  (Volume:6 ,  Issue: 2 )