Real-time Software Modelling using Statecharts and Timed Automata Approaches

Statecharts are commonly used in the specification of reactive systems. They are useful in introducing modular and hierarchical features to classical finite-state machines (FSMs). UML statecharts are gaining popularity for the modelling of real-time embedded software. However, UML statecharts are weak in their support for absolute time and they do not formally support verification methods. Timed automata models, on the other hand, are rich in support of real-time modelling and support formal verification solutions. In this paper the statechart method and the timed automata method are compared. A case study model for an ATM output buffer switch is developed and the models are presented