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A Bit-Width Optimization Methodology for Polynomial-Based Function Evaluation

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2 Author(s)
Lee, D.-U. ; Dept. of Electr. Eng., California Univ., Los Angeles, CA ; Villasenor, J.D.

We present an automated bit-width optimization methodology for polynomial-based hardware function evaluation. Due to the analytical nature of the approach, overflow protection and precision accurate to one unit in the last place (ulp) can be guaranteed. A range analysis technique based on computing the root of the derivative of a signal is utilized to determine the minimal number of integer bits. Fractional bit requirements are established using an analytical error expression derived from the functions that occur along the data path. Global fractional bit optimization across multiple computation stages is performed using simulated annealing and circuit area estimation functions

Published in:

Computers, IEEE Transactions on  (Volume:56 ,  Issue: 4 )

Date of Publication:

April 2007

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