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Design of efficient modulo 2n + 1 multipliers

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2 Author(s)
Vergos, H.T. ; Comput. Eng. & Informatics Dept., Univ. of Patras ; Efstathiou, C.

A new modulo 2n+1 multiplier architecture is proposed for operands in the weighted representation. A new set of partial products is derived and it is shown that all required correction factors can be merged into a single constant one. It is also proposed that part of the correction factor is treated as a partial product, whereas the rest is handled by the final parallel adder. The proposed multipliers utilise a total of (n+1) partial products, each n bits wide and are built using an inverted end-around-carry, carry-save adder tree and a final adder. Area and delay qualitative and quantitative comparisons indicate that the proposed multipliers compare favourably with the earlier solutions

Published in:

Computers & Digital Techniques, IET  (Volume:1 ,  Issue: 1 )