Analysis of Crosstalk and Process Variations Effects on On-Chip Interconnects

We present analysis of crosstalk and process variations effects on reliability and signal propagation delay of two delay-insensitive on-chip interconnects. The first interconnect is designed using conventional two-phase dual-rail encoding using voltage-mode signaling. The second one uses current-mode signaling with new implementation of two-phase dual-rail encoding. It uses multi-current level and differential switching of dual-rail wires to indicate the data value and its validity respectively. Performance comparison between the two interconnects shows the novel differentially switching dual-rail link is faster compared to the conventional two-phase dual-rail one. The effect of crosstalk is analyzed using 4-bit parallel data transfer using transmission line model with capacitive and inductive coupling and 16 different switching patterns. We analyze the effect of process variations on reliability and delay in the presence of crosstalk by changing wire width by plusmn10% and thickness by -10%. In addition the effect of plusmn3sigma supply voltage variation on delay is studied. The circuit is designed and simulated using Cadence Analog Spectre and Hspice of 130nm CMOS technology