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A High-Throughput Network-on-Chip Architecture for Systems-on-Chip Interconnect

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2 Author(s)
A. Bouhraoua ; Computer Engineering Department, King Fahd University of Petroleum and Minerals, P.O.Box 969, Dhahran, 31261, Saudi Arabia. Email: ; M. E. Elrabaa

A buffer-less, contention-free, network-on-chip architecture based on a modified fat tree is proposed. Simulations results show that the proposed architecture achieves maximum throughput (> 90%) way above the 40-50% seen in conventional fat trees. Contention is eliminated and latency is reduced through an improved topology and router architecture. Area of the network is kept to a minimum by pushing the buffers to the edge of the network at the client interface. Simulation results show that the required number of buffers at the client interface is a fraction of the theoretical maximum. This means that the actual number of buffers can be tailored to suit a class of applications running on a specific platform

Published in:

2006 International Symposium on System-on-Chip

Date of Conference:

13-16 Nov. 2006