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Comparison of a Timing-Error Tolerant Scheme with a Traditional Re-transmission Mechanism for Networks on Chips

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7 Author(s)

On-chip wires are becoming unreliable as the effect of various noise sources increases with technology scaling. This leads to unpredictable timing delay variations on the interconnect wires. There is a significant need to mitigate the effect of parasitics on the interconnects, while keeping performance and area overheads at a minimum. In this work, the authors present a timing error tolerant design methodology, T-error, that provides dynamic recovery from timing delay variations on the interconnects. The authors validate the functionality of the T-error methodology using cycle-accurate RTL models of a network-on-chip (NoC) design, that are integrated onto a multiprocessor virtual platform. The comparisons with the state-of-the-art error recovery mechanisms show that the T-error system provides error recovery with higher performance than the existing schemes. The authors also present the synthesis results for the T-error scheme, which show that the scheme has negligible overhead

Published in:

2006 International Symposium on System-on-Chip

Date of Conference:

13-16 Nov. 2006