High Speed Search Algorithms for Block-Based Motion Estimation Video Compression

The enormous computations associated with motion estimation prevent software implementations from running in real time. A hardware implementation to achieve real time video compression was demonstrated utilizing mentor graphics tools. Several block-matching criteria and architectures were developed to improve the hardware efficiency and computational speed of block-matching VLSI chips. The VHDL code for block-based motion estimation was designed using high speed arithmetic units. As the complexity of motion estimation is greatly influenced by the search algorithm and search range, the design focuses mainly on the high throughput rate and scalability for increased search ranges. The design was simulated for different image sizes at different clock frequencies with varying block sizes and search areas. The paper details the search algorithms and simulation results in order to achieve high speed hardware processing. With a clock frequency of 400MHz, the estimated time for motion estimation for QCIF and CIF sequences shows the feasibility for real-time video-codec