By Topic

HW/SW Co-Design and Implementation of Multi-Standard Video Decoding

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Liu Feng ; Microprocessor Res. & Dev. Center, Peking Univ., Beijing ; Guo Rui ; Shi Shu ; Cheng Xu

In this paper, we present a design and implementation of multi-standard video decoder, which adopts the principle of HW/SW cooperation to achieve real time video decoding process. Based on the profiling of MPEG-1/2/4 video decoding algorithms, the computational intensive IDCT and sub-pixel interpolation are figured out to implement with hardware, and the dedicated DMA channels are provided to fulfil the high throughput of MC processing. The remained decoding functions are realized with software based on a RISC CPU. The design shares the advantage of high flexibility to fulfil multi-standard processing. With the assistant hardware accelerating, the proposed video decoder can achieve the MPEG-1/2/4 D1 size (720times480) video decoding at 30 fps

Published in:

Embedded Systems for Real Time Multimedia, Proceedings of the 2006 IEEE/ACM/IFIP Workshop on

Date of Conference:

Oct. 2006