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A Layered Finite Element Method for High-Frequency Modeling of Large-Scale Three-Dimensional On-Chip Interconnect Structures

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3 Author(s)
Dan Jiao ; Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN ; Chakravarty, S. ; Changhong Dai

This paper proposes a high-capacity electromagnetic solution, layered finite element method, for high-frequency modeling of large-scale 3D on-chip interconnect structures. In this method, first, the matrix system of the original 3D problem is reduced to that of 2D layers. Second, the matrix system of 2D layers is further reduced to that of a single layer. Third, an algorithm of logarithmic complexity is proposed to further speed up the analysis for periodic interconnect structures. The entire procedure is numerically rigorous without making any theoretical approximation. The computational complexity only involves solving a single layer irrespective of the original problem size. Hence, the proposed method is equipped with a high capacity to solve large-scale IC problems. The proposed method was used to simulate a set of large-scale interconnect structures that were fabricated on a test chip using conventional Si processing techniques. Excellent agreement with the measured data has been observed from DC to 50GHz

Published in:

Electrical Performance of Electronic Packaging, 2006 IEEE

Date of Conference:

Oct. 2006