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Grand Challenge: The Future of CMOS System-on-Chip Hardware and Software Application Development

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2 Author(s)
Brian Von Herzen ; IEEE Members, Rapid Prototypes, Inc. ; Mike Lerer

CMOS technology trends are forcing system designers to use multiple processors on a single die to meet power performance objectives. Power performance optimization also leads to heterogeneous combinations of processors, DSP units, ASSPs and FPGAs. Both of these trends exacerbate the crisis in software productivity. New tools, languages and implementation techniques must be utilized to ensure achievement of time-to-market objectives for today's system-on-chip designs. Several examples are included to illustrate the problems, issues and opportunities as systems on chips drive towards hundreds of concurrent processes. These issues and their successful resolution are expected to cut across hardware and software boundaries and pervade the electronics industry as the drive for power performance continues over the coming decade

Published in:

2006 IEEE Dallas/CAS Workshop on Design, Applications, Integration and Software

Date of Conference:

Oct. 2006