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High Throughput, Parallel, Scalable LDPC Encoder/Decoder Architecture for OFDM Systems

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3 Author(s)
Yang Sun ; Department of Electrical and Computer Engineering, Rice University, Houston, TX, 77005. ; Marjan Karkooti ; Joseph R. Cavallaro

This paper presents a high throughput, parallel, scalable and irregular LDPC coding and decoding system hardware implementation that supports twelve combinations of block lengths 648, 1296, 1944 bits and code rates 1/2, 2/3, 3/4, 5/6 based on IEEE 802.11n standard. Based on architecture-aware LDPC codes, we propose an efficient joint LDPC coding and decoding hardware architecture. The prototype architecture is being implemented on FPGA and tested over the air on our wireless OFDM testbed, which is a highly capable, scalable and extensible platform for advanced wireless research. The ASIC resource requirements of the decoder are reported and a trade-off between pipelined and non-pipelined implementation is described

Published in:

2006 IEEE Dallas/CAS Workshop on Design, Applications, Integration and Software

Date of Conference:

Oct. 2006