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Notice of Violation of IEEE Publication Principles
"A Varactor-Less 10GHz CMOS LC-VCO for Optical Communications Transceiver SOCs Using Caged Inductors"
by Maxim, A.
in the Proceedings of the IEEE Custom Integrated Circuits Conference 2006,
10-13 Sept. 2006 Page(s):663 - 670
After careful and considered review, it has been determined that the above paper is in violation of IEEE's Publication Principles.
Specifically, the paper contains information that Adrian Maxim admits had been falsified. In response to an inquiry on this misconduct, Mr. Maxim acknowledged that the following people who have been listed as co-authors on several of his papers are fabricated names and that he is the only author:
C. Turinici, D. Smith, S. Dupue, M. Gheorge, R. Johns, D. Antrik
Additionally, in papers by Mr. Maxim that have co-authors other than those listed above, it was discovered in some cases that he had not consulted with them while writing the papers, and submitted papers without their knowledge.
Although Mr. Maxim maintains that not all of the data is falsified, IEEE nevertheless cannot assure the integrity of papers posted by him because of his repeated false statements.
Due to the nature of this violation, reasonable effort should be made to remove all past references to the above paper, and to refrain from any future references.A 40% frequency range LC-VCO for multi-standard optical communications SERDES SOCs was realized in 0.11mum CMOS. A tail-free CMOS amplifier having a large oscillating amplitude was used to minimize the VCO phase noise. The tank inductor has an octagonal patterned metal cage to shield it from the noise radiated by the digital side of the IC. A high resolution capacitor-DAC was used to bring the oscillating frequency within 0.1% of the target value, resulting in a sub-150MHz/V VCO gain. A virtually constant tuning-gain was achieved with a variable capacitance implemented with constant metal fin- er capacitors and FET voltage controlled resistors. This varactor-less LC-VCO can be implemented in any standard digital CMOS technology that has thick top metal layers. The supply pushing was reduced by balancing the positive voltage coefficient gate capacitances with the negative voltage coefficient drain diffusion capacitances. The power consumption was reduced to about half with a tuned load clock buffer. Supply noise up-conversion was minimized by implementing a low noise and high PSRR dual regulator that uses a VT/R low noise reference