Referenced Items are not available for this document.
A low-power, area-efficient 128-bit multifunction arithmetic unit has been developed for programmable shaders for handheld 3D graphics systems. It adopts the logarithmic number system (LNS) at the arithmetic core for the single cycle throughput and the small-size low-power unification of various complex arithmetic operations such as power, logarithm, trigonometric functions, vector multiplication, division, square root and inner product. An uneven 24-piecewise logarithmic conversion scheme is proposed with 0.8% of maximum conversion error. A 93K gate test chip is fabricated with 0.18-mum CMOS technology. It operates at 210MHz with 15.3mW power consumption at 1.8V
Published in:
Custom Integrated Circuits Conference, 2006. CICC '06. IEEE
Date of Conference: 10-13 Sept. 2006
- Page(s):
- 535 - 538
- E-ISBN :
- 1-4244-0076-7
- Print ISBN:
- 1-4244-0075-9
- INSPEC Accession Number:
- 9464635
- Conference Location :
- San Jose, CA
- Digital Object Identifier :
- 10.1109/CICC.2006.320921
- Product Type:
- Conference Publications
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