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VLSI Design of High-Rate Quasi-Cyclic LDPC Codes for Magnetic Recording Channel

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3 Author(s)
Hao Zhong ; Dept. of Electron. Comput. & Sci. Eng., Rensselaer Polytech. Inst., Troy, NY ; Tong Zhang ; Haratsch, E.F.

By implementing an FPGA-based simulator, this paper investigates the semi-random construction of high-rate regular QC-LDPC codes with low error floor for the magnetic recording channel. Then a new QC-LDPC decoder hardware architecture is proposed. Finally, a read channel signal processing datapath consisting of a parallel Max-Log-MAP detector and the proposed QC-LDPC decoder is implemented in 0.13 mum CMOS. This design achieves a throughput up to 1.8Gbps under 16 iterations of LDPC decoding

Published in:

Custom Integrated Circuits Conference, 2006. CICC '06. IEEE

Date of Conference:

10-13 Sept. 2006