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By implementing an FPGA-based simulator, this paper investigates the semi-random construction of high-rate regular QC-LDPC codes with low error floor for the magnetic recording channel. Then a new QC-LDPC decoder hardware architecture is proposed. Finally, a read channel signal processing datapath consisting of a parallel Max-Log-MAP detector and the proposed QC-LDPC decoder is implemented in 0.13 mum CMOS. This design achieves a throughput up to 1.8Gbps under 16 iterations of LDPC decoding
Published in:
Custom Integrated Circuits Conference, 2006. CICC '06. IEEE
Date of Conference: 10-13 Sept. 2006
- Page(s):
- 325 - 328
- E-ISBN :
- 1-4244-0076-7
- Print ISBN:
- 1-4244-0075-9
- INSPEC Accession Number:
- 9464605
- Conference Location :
- San Jose, CA
- Digital Object Identifier :
- 10.1109/CICC.2006.320902
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