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A 32Gb/s On-chip Bus with Driver Pre-emphasis Signaling

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6 Author(s)
Liang Zhang ; Dept. of Electr. 7 Comput. Eng., North Carolina State Univ., Raleigh, NC ; Wilson, J. ; Bashirullah, R. ; Lei Luo
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A 16-bit on-chip bus with driver pre-emphasis fabricated in 0.25mum CMOS technology attains an aggregate signaling data rate of 32Gb/s over 5-10mm long lossy interconnects while reducing delay latency by 28.3%, power by 15.0%, and peak current by 70% over a conventional single-ended voltage-mode static bus. The proposed bus is robust against crosstalk noise and occupies comparable routing area to a reference static bus design

Published in:

Custom Integrated Circuits Conference, 2006. CICC '06. IEEE

Date of Conference:

10-13 Sept. 2006