A 32Gb/s On-chip Bus with Driver Pre-emphasis Signaling

A 16-bit on-chip bus with driver pre-emphasis fabricated in 0.25μm CMOS technology attains an aggregate signaling data rate of 32Gb/s over 5-10mm long lossy interconnects while reducing delay latency by 28.3%, power by 15.0%, and peak current by 70% over a conventional single-ended voltage-mode static bus. The proposed bus is robust against crosstalk noise and occupies comparable routing area to a reference static bus design.