Referenced Items are not available for this document.
A 16-bit on-chip bus with driver pre-emphasis fabricated in 0.25mum CMOS technology attains an aggregate signaling data rate of 32Gb/s over 5-10mm long lossy interconnects while reducing delay latency by 28.3%, power by 15.0%, and peak current by 70% over a conventional single-ended voltage-mode static bus. The proposed bus is robust against crosstalk noise and occupies comparable routing area to a reference static bus design
Published in:
Custom Integrated Circuits Conference, 2006. CICC '06. IEEE
Date of Conference: 10-13 Sept. 2006
- Page(s):
- 265 - 268
- E-ISBN :
- 1-4244-0076-7
- Print ISBN:
- 1-4244-0075-9
- INSPEC Accession Number:
- 9454269
- Conference Location :
- San Jose, CA
- Digital Object Identifier :
- 10.1109/CICC.2006.320855
- Product Type:
- Conference Publications
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