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A CMOS 15-Bit 125-MS/s Time-Interleaved ADC with Digital Background Calibration

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3 Author(s)
Zwei-Mei Lee ; Dept. of Electron. Eng., Nat. Chiao-Tung Univ., Hsin-Chu ; Cheng-Yeh Wang ; Jieh-Tsorng Wu

A 15-bit 125-MS/s two-channel time-interleaved pipelined ADC is fabricated in a 0.18 mum CMOS technology, and achieves 91.9 dB SFDR, 69.9 dB SNDR for a 9.99 MHz input. The ADC uses a single sample-and-hold amplifier which employs a precharging circuit technique to mitigate the performance requirements for its opamp. Digital background calibration is applied to maintain the conversion linearity of each A/D channel and also correct both gain and offset mismatches between the two channels. Excluding I/O buffers, the chip occupies an area of 4.3 times 4.3 mm 2 and dissipates 909 mW from a 1.8 V supply

Published in:

Custom Integrated Circuits Conference, 2006. CICC '06. IEEE

Date of Conference:

10-13 Sept. 2006