Embedded Mixed-Signal IP Development Methodology in 90nm CMOS SerDes FPGAs

A 275mW at 6.375Gbps high speed serial interface developed in TSMC's 90nm triple-gate oxide CMOS process and the customized methodology applied to develop and integrate high-speed mixed-signal IPs into FPGA platforms is presented. The risk reduction approach used ensured reliable product, with timely availability. The transceiver IP supports multiple protocols such as PCIe, XAUI, CEI, SDI, etc. There are as many as 20 Rx/Tx transceiver channels embedded in the FPGA. The transceiver achieves better than 10
^-12
BER at 6.375Gbps across the XAUI backplane originally designed for 3.125Gbps