By Topic

Embedded Mixed-Signal IP Development Methodology in 90nm CMOS SerDes FPGAs

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Patel, R.H. ; Altera Corp., San Jose, CA ; Bereza, W.

A 275mW at 6.375Gbps high speed serial interface developed in TSMC's 90nm triple-gate oxide CMOS process and the customized methodology applied to develop and integrate high-speed mixed-signal IPs into FPGA platforms is presented. The risk reduction approach used ensured reliable product, with timely availability. The transceiver IP supports multiple protocols such as PCIe, XAUI, CEI, SDI, etc. There are as many as 20 Rx/Tx transceiver channels embedded in the FPGA. The transceiver achieves better than 10-12 BER at 6.375Gbps across the XAUI backplane originally designed for 3.125Gbps

Published in:

Custom Integrated Circuits Conference, 2006. CICC '06. IEEE

Date of Conference:

10-13 Sept. 2006