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Low Leakage SOI CMOS Static Memory Cell With Ultra-Low Power Diode

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3 Author(s)
Levacq, D. ; DICE, Univ. Catholique de Louvain, Louvain-la-Neuve, Belgium ; Dessard, V. ; Flandre, D.

A new CMOS digital storage device is developed based on the combination of two reverse biased composite CMOS diodes, each of them featuring ultra-low leakage and a negative impedance characteristic in reverse mode. The biasing of MOS transistors in very weak inversion, with negative gate-to-source voltages, results in a static current that lays orders of magnitude below that of conventional cross-coupled CMOS inverters. Based on our device, a 7-transistors SRAM cell is presented. Modeling, simulation and experimental characterization of the main properties of this cell are reported for a 0.13 mum partially-depleted SOI CMOS process. The feasibility of ultra-low leakage memory circuits is demonstrated experimentally by the design of a 256 times 1 bits SRAM column.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:42 ,  Issue: 3 )