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Impact of High- \kappa Offset Spacer in 65-nm Node SOI Devices

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8 Author(s)
Ming-Wen Ma ; Inst. of Electron., Nat. Chiao Tung Univ., Hsinchu ; Chien-Hung Wu ; Tsung-Yu Yang ; Kuo-Hsing Kao
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In this letter, 65-nm node silicon-on-insulator devices with high-kappa offset spacer dielectric were investigated by extensive 2-D device simulation. The result shows that the high-kappa offset spacer dielectric can effectively increase the on-state driving current ION and reduce the off leakage current IOFF due to the high vertical fringing electric field effect. This fringing field can significantly improve the ION/IOFF current ratio and the subthreshold swing compared with the conventional oxide spacer. Consequently, the gate-to-channel control ability is enhanced by the fringing field via the high-kappa offset spacer dielectric

Published in:

Electron Device Letters, IEEE  (Volume:28 ,  Issue: 3 )

Date of Publication:

March 2007

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