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Formal Model of Data Reuse Analysis for Hierarchical Memory Organizations

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3 Author(s)
Ilie I. Luican ; Dept. of Computer Science, University of Illinois at Chicago, Chicago, IL 60607, U.S.A. ; Hongwei Zhu ; Florin Balasa

In real-time data-dominated communication and multimedia processing applications, due to the manipulation of large sets of data, a multi-layer memory hierarchy is used to enhance the system performance and also to reduce the energy consumption. Savings of dynamic energy can be obtained by accessing frequently used data from smaller memories rather than from large background memories. The optimization of the hierarchical memory architecture implies the addition of layers of smaller memories to which heavily used data can be copied. This paper presents a formal model for data reuse analysis which identifies those parts of arrays more intensely accessed, taking also into account the relative lifetimes of the signals. Tested on a two-layer memory hierarchy, this model led to savings in the dynamic energy from 40% to over 70% relative to the energy used in the case of a flat memory design

Published in:

2006 IEEE/ACM International Conference on Computer Aided Design

Date of Conference:

5-9 Nov. 2006