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Optimal Memoryless Encoding for Low Power Off-Chip Data Buses

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3 Author(s)
Yeow Meng Chee ; School of Physical & Mathematical Sciences, Nanyang Technological University, Singapore 637616; Card View Pte. Ltd., 41 Science Park Road, #04-08A The Gemini, Singapore Science Park II, Singapore 117610. ymchee@alumni.uwaterloo.ca ; Charles J. Colbourn ; Alan C. H. Ling

Off-chip buses account for a significant portion of the total system power consumed in embedded systems. Bus encoding schemes have been proposed to minimize power dissipation, but none has been demonstrated to be optimal with respect to any measure. In this paper, we give the first provably optimal and explicit (polynomial-time constructible) families of memoryless codes for minimizing bit transitions in off-chip buses. Our results imply that having access to a clock does not make a memoryless encoding scheme that minimizes bit transitions more powerful

Published in:

2006 IEEE/ACM International Conference on Computer Aided Design

Date of Conference:

5-9 Nov. 2006