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Design optimization for single-event upset robustness using simultaneous dual-VDD and sizing techniques

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3 Author(s)
Choudhury, M.R. ; Dept. of Electr. & Comput. Eng., Rice Univ., Houston, TX ; Quming Zhou ; Mohanram, K.

An optimization algorithm for the design of combinational circuits that are robust to single-event upsets (SEUs) is described. A simple, highly accurate model for the SEU robustness of a logic gate is developed. This model - in posynomial form - is integrated with performance and power constraints into an optimization framework based on geometric programming for design space exploration. Simulation results for design optimization using simultaneous dual-VDD and gate sizing techniques for the 70 nm process technology demonstrate the tradeoffs that can be achieved with this approach

Published in:

Computer-Aided Design, 2006. ICCAD '06. IEEE/ACM International Conference on

Date of Conference:

5-9 Nov. 2006