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Testing Delay Faults in Asynchronous Handshake Circuits

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2 Author(s)
Feng Shi ; Electrical Engineering Dept., Yale University, New Haven, Connecticut. feng.shi@yale.edu ; Yiorgos Makris

As a class of asynchronous circuits, handshake circuits are designed to tolerate variation of gate delays. However, certain timing constraints, such as the bundled data assumption, are exploited in the single-rail implementation of these circuits in order to simplify them. Therefore, any delay fault in the circuit may cause one of two problems, namely performance degradation or logic errors. To address the challenges incurred by the autonomous behavior of handshake circuits during at-speed test, we propose test methods for both types of delay faults based on a DFT strategy which greatly simplifies the complexity of test generation. The efficiency of the proposed methodology is demonstrated through experimental results on several handshake circuits

Published in:

2006 IEEE/ACM International Conference on Computer Aided Design

Date of Conference:

5-9 Nov. 2006