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High Performance and High Efficiency Memory Management System for H.264/AVC Application in the Dual-Core Platform

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4 Author(s)
Nai-Ran Zhang ; VLSI & System Lab, Beijing University of Technology, Beijing, China ; Mo Li ; Yang-yang Li ; Wu-Chen Wu

This paper proposes memory management system for multimedia application based on dual-core platform. To use memory bus bandwidth efficiently and reduce memory bus transition, two steps store optimization in control level is adopted and bus efficiency increases nearly 35% compared with former scheme. To harmonize different master requirement, reasonable schedule level arranges memory access priority. Under these two levels, memory controller can cope with H.264 HDTV decoder 1920times1080 @ 30 frames per sec real time access clocking at 100 MHz. Moreover, this VLSI design is convenient to be integrated into different multimedia processing platform

Published in:

2006 SICE-ICASE International Joint Conference

Date of Conference:

18-21 Oct. 2006