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1V high-speed digital circuit technology with 0.5μm multi-threshold CMOS

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5 Author(s)
Mutoh, S. ; NTT LSI Lab., Kanagawa, Japan ; Douseki, T. ; Matsuya, Y. ; Aoki, T.
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A 1-V high-speed and low-power digital circuit technology with 0.5μm multi-threshold CMOS (MT-CMOS) is proposed. This technology applies both low-threshold voltage and high-threshold voltage MOSFETs in one LSI. Low-threshold voltage MOSFETs enhance speed performance at a supply voltage of 1 V or less. High-threshold voltage MOSFETs suppress the stand-by leakage circuit during the sleep period. The technology has achieved logic gate characteristics of a 1.7-ns propagation delay time and 0.3-μW/MHz/gate power dissipation. To demonstrate its effectiveness, a standard cell based PLL-LSI was designed as a carrying vehicle. An 18-MHz operation at 1 V was obtained using a 0.5-μm MT-CMOS process

Published in:

ASIC Conference and Exhibit, 1993. Proceedings., Sixth Annual IEEE International

Date of Conference:

27 Sep-1 Oct 1993