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Energy Conscious Simultaneous Voltage Scaling and On-chip Communication Bus Synthesis

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3 Author(s)
Sujan Pandey ; Institute of Microelectronics Systems, Karlstr. 15, D-64283, Darmstadt, Darmstadt University of Technology, Germany. pandey@mes.tu-darmstadt.de ; Tudor Murgan ; Manfred Glesner

Due to the ever increasing trend of system complexity and technology scaling, synthesizing on-chip communication architecture appears to be a challenging task for the system designers. The traditional approaches are mostly based on the simulation of an entire system. However, the resulting architecture may not fulfil the requirements such as the performance, energy, size etc. and the computational cost of simulation based techniques is infeasible when exploring a large design space. This paper presents a simultaneous on-chip communication bus synthesis and voltage scaling approach, which is modeled in NLP (nonlinear programming) and finds an energy efficient minimum number of bus(es) and an optimal size of bus width by simultaneously performing resource selection, scheduling, binding and voltage scaling of an on-chip bus. The voltages (supply and body bias) are scaled to reduce the total energy consumption of a bus by exploiting the slack of each on-chip module. The experimental results conducted on real-life examples, demonstrate the synthesis of an energy efficient communication bus with total energy saving up to 57.1% by scaling its supply and body bias voltages

Published in:

2006 IFIP International Conference on Very Large Scale Integration

Date of Conference:

16-18 Oct. 2006