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A graph-coloring approach to the allocation and tasks scheduling for reconfigurable architectures

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4 Author(s)
Marco Giorgetta ; Politecnico di Milano, Dipartimento di Elettronica e Informazione, Via Ponzio 34/5, 20133 Milano, Italy. ; Marco Santambrogio ; Donatella Sciuto ; Paola Spoletini

Designing systems mapped onto FPGAs that foresee a dynamic reconfiguration of the application is a difficult task. It requires that the identification of the reconfigurable tasks and their allocation onto the FPGA must be defined during the design phases. Furthermore, also the schedule of dynamic reconfigurations must be defined. This paper presents an improved scheduling and allocation of reconfigurable tasks onto an FPGA, based on the coloring problem. The proposed algorithm stems from the one previously presented (Ferrandi et al., 2005), but introduces backtracking to improve the performance in terms of number of number of colors, that represent FPGAs areas. The new algorithm has been experimented on the Xilinx-based architecture defined to support dynamic reconfigurability (Donato et al., 2005)

Published in:

2006 IFIP International Conference on Very Large Scale Integration

Date of Conference:

16-18 Oct. 2006