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State-holding in Look-Up Tables: application to asynchronous logic

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4 Author(s)
Laurent Fesquet ; TIMA Laboratory 46, avenue Félix Viallet 38031 Grenoble, France. Laurent.Fesquet@imag.fr ; Bertrand Folco ; Mathieu Steiner ; Marc Renaudin

The integrated systems today require flexibility, performance and reconfigurability. The trends in this domain lead to integrate on a single chip different processing cores, communication units and reconfigurable logic. Therefore the systems-on-chip (SoC) can embed programmable logic. In order to challenge the reconfigurability paradigm for special issues such as communication, synchronization or security, the asynchronous logic is a very promising approach. Nevertheless, the standard programmable logic blocks are not well-suited to map asynchronous circuits. The goal of this study is to define a more adequate programmable structure to implement asynchronous designs on SoCs embedding a reconfigurable part. This work is part of a larger project which includes the design of an embedded programmable logic device (e-PLD) dedicated to the implementation of clockless circuits. The more robust and reliable asynchronous circuits are quasi-delay insensitive. These circuits are mainly constructed with Muller gates. The paper presents a new look-up table (LUT) architecture well-adapted to the Muller gate implementation. This new LUT allows the combination of a single memory-point with combinational logic. This programmable memory is realized thanks to an optional feedback structure. This architecture has been evaluated in CMOS, pass-transistor logic and 3-state logic which is a non-conventional way to design LUTs. The simulations report detailed comparisons between the different logic styles and demonstrate for equivalent power consumption a higher speed for 3-state logic

Published in:

2006 IFIP International Conference on Very Large Scale Integration

Date of Conference:

16-18 Oct. 2006