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Improved Phase-Locked Loop Performance with Adaptive Phase Comparators

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2 Author(s)
Eijselendoorn, J. ; Philips Data Systems ; den Dulk, R.C.

A major problem in phase-locked loop (PLL) design is to meet the requirements of both fast signal acquisition and good synchronous mode performance. This relation is reviewed for different types of phase comparators. As a result a new phase-and-frequency comparator is proposed. This comparator is based on an up-down counter principle and can be considered as an adaptive acquisition control circuit. The analysis of a PLL with the proposed phase comparator is based on an exact calculation method for the pull-in time. It is shown that fast signal acquisition is possible without affecting the filtering properties of the loop. Experimental results are given of the acquisition behavior of a second-order type-2 loop which show a good correspondence with the theoretical analysis.

Published in:

Aerospace and Electronic Systems, IEEE Transactions on  (Volume:AES-18 ,  Issue: 3 )

Date of Publication:

May 1982

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