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A Numerical Study of Board-level Stacked-die Packages Under Coupled Power and Thermal Cycling Test Conditions

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4 Author(s)
Tong Hong Wang ; Advanced Semiconductor Engineering, Inc., 26 Chin 3rd Rd., Nantze Export Processing Zone, Nantze, Kaohsiung, Taiwan, R.O.C. ; Chang-Chi Lee ; Ching-Chun Wang ; Yi-Shao Lai

In this study, the sequential thermal-mechanical coupling analysis, which solves in turn the transient temperature field and subsequent thermomechanical deformations, is performed to investigate thermal characteristics along with fatigue reliability of board-level stacked-die thin-profile fine-pitch ball grid array chip-scale packages under coupled power and thermal cycling test conditions. Effects of different power dissipation conditions are examined and compared

Published in:

2006 International Microsystems, Package, Assembly Conference Taiwan

Date of Conference:

18-20 Oct. 2006