Study of a SONET STS-3c based ATM user network interface design

The authors analyze the serial and parallem implementation of a SONET STS-3c based asynchronous transfer mode (ATM) user network interface design. The tradeoffs between both serial and parallel desings of the SONET scrambler and the ATM physical layer cyclic redundancy code (CRC) generator are analyzed in terms of gate count and power dissipation. The result of the analysis shows that an 8-b parallel processing of the ATM header CRC and the SONET scrambler offers the optimal solution in terms of performance and cost of implementation.<
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