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A CMOS phase detector for mixed signal ASIC application

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1 Author(s)
Comer, D.T. ; Penn State Harrisburg, Middletown, PA, USA

The author presents a phase detector that is constructed using a type of current mode logic. The resulting design can be fabricated on a conventional CMOS process but exhibits performance that is approximately two times faster than a similar design based upon conventional CMOS logic circuits. At the same time the low voltage swings of the current mode logic produce low parasitic coupling energy, allowing for good compatability with analog cells. The new design is intended for phase locked loop applications n the 25-50 MHz range but may be useful as a standard ASIC building block in other mixed signal applications

Published in:

ASIC Conference and Exhibit, 1993. Proceedings., Sixth Annual IEEE International

Date of Conference:

27 Sep-1 Oct 1993